hi-8010/hi-8110 series the hi-8010 & hi-8110 high voltage display drivers are constructed of mos p channel and n channel enhancement mode devices in a single monolithic structure. they are designed to drive high voltage liquid crystal displays by converting low level input signals (ttl on the hi-8010 and cmos on the hi-8110) to high voltage drive signals. both devices can drive up to 38 segments and require minimal display-to-data source interfacing. serial data is loaded and held in internal latches until new display data is received. the hi-8010 & hi-8110 are available in a variety of ceramic and plastic packaging including leaded and leadless chip carriers; and j-lead and gull-wing quad flat packs. dichroic liquid crystal displays standard liquid crystal displays vacuum fluorescent displays mems drivers applications 5 volt input translated to 30 volts or less pin-out adaptable to drive 30, 32 or 38 lcd segments rc oscillator or high voltage (bp) clock input ttl compatible inputs (hi-8010 only) cmos compatible inputs (hi-8110 only) low power consumption industrial (-40c to +85c) & military (-55c to +125c) temperature ranges pin for pin compatible with the micrel mic8010/8011 series and the ami s4520 series drivers cascadable military level processing available pin configuration (top view) functional block diagram bp oscillator divider voltage translator high voltage buffer 38 stage shift register 38 bit latch voltage translators high voltage drivers segments data in clk le dout 38 dout 32 dout 30 general description din cl cs ld lcd? lcd? opt (see page 5 for additional package pin configurations) features cmos high voltage display driver august 2006 39 38 37 36 35 34 33 32 31 30 29 28 s26 s25 s24 s23 s22 s21 s20 dout 38 n/c n/c n/c bp s19 2 3 4 5 6 7 8 9 10 11 12 ld din lcd? lcd?opt v s37 s38 s1 s2 s3 s4 s5 s6 dd s7 s8 s9 s10 s11 s12 s13 s14 v s15 s16 s17 s18 ee 14 15 16 17 18 19 20 21 22 23 24 25 26 51 50 49 48 47 46 45 44 43 42 41 40 cl cs v s36 s35 s34 s33 s32 s31 s30 s29 s28 s27 ss hi-8010pqi hi-8110pqi hi-8010pqt & hi-8110pqt 52 - pin plastic p qf holt integrated circuits www.holtic.com (ds8010, rev. e) 08/06
functional description whenever a logic "0" is applied to the chip select ( ) input, one bit of data is clocked into the shift register from the serial data input (din) with each negative transition of the clock ( ) input. is internally tied to vss on some versions. a logic "1" present at the load (ld) input will cause a parallel transfer of data from the shift register to the data latch. if the load (ld) input is held high while data is clocked into the shift register, the latch will be transparent. to display segments, a logic "1" is stored in the appropriate shift register bit position, and the segment output is out-of- phase with the backplane. the backplane output functions in 1 of 2 modes; externally driven or self-oscillating. when the lcd? input is externally driven with the lcd?opt input open circuit (figure 2), the backplane output will be in-phase with lcd?. utilizing the self-oscillating mode, inputs lcd? and lcd?opt are tied together and connected to an rc circuit (figure 3). a 150k resistor with a 470pf capacitor generates an approximate backplane frequency of 100hz. the lcd?/lcd?opt oscillator frequency is divided by 256 to determine the backplane output frequency. the resistor value (r) must be at least 30k for proper self-oscillator operation. for displays having a number of segments greater than 38, two or more of the display drivers may be cascaded together by connecting the serial data output (dout) from the first driver, to the serial data input (din) of the following driver, etc. (see figures 2 & 3). data out (dout) will change state cs cl cs all four logic inputs are ttl compatible on the hi-8010 and cmos compatible on the hi-8110. hi-8010/hi-8110 series internal oscillator circuit to backplane translator and driver 256 c r lcd? opt lcd? figure 1 q on the rising edge of the clock ( ). clock ( ), load (ld) and chip select ( ) should be tied in common with each other, respectively, between all cascaded display drivers. cl cl cs holt integrated circuits 2 symbol function description vss power 0 volts input logic input chip select input logic input clocks shift register on negative edge and dout pins on positive edge ld input logic input segment outputs equal shift register data if load is high din input logic input shift register data input lcd0 input analog input display clock input and is always bonded out. can swing from vee to vdd lcd0opt output analog output bonded out only if an rc oscillator is required vdd power 5 volts vee power 0 volts to -30 volts dout output logic output selected pinout can provide shift register taps at positions 30, 32, 34, or 38 bp output display drive output low resistance drive for the backplane and swings from vdd to vee segments output display drive output high resistance drive for each segment and swings from vdd to vee cs cl pin descriptions
hi-8010/hi-8110 series parameter symbol condition min typ max units operating voltage vdd 3.0 7.0 v supply current idd static, no load 200 a iee static, no load f =100hz 150 a input low voltage, hi-8010 (except lcd?) vil 0 0.8 v input high voltage, hi-8010 (except lcd?) vih 2 vdd v input low voltage, hi-8110 (except lcd ) vil 0 0.3 vdd v input high voltage, hi-8110 (except lcd input low voltage (lcd?) vilx vee 3 v input high voltage (lcd?) vihx 3.5 vdd v input current iin vi n=0to5v 1 a input capacitance (not tested) ci 5 pf segment output impedance rseg il = 10a 10 15 k backplane output impedance rbp il = 10a @ 25c 450 600 data out current: idoh source current, voh = 4.5v -0.6 ma idol sink current, vol = 0.5v 0.6 ma bp ttl ttl cmos ? ?) vih 0.7 vdd vdd v cmos dc electrical characteristics vdd = 5v, vee = -25v, vss = 0v, ta = operating temperature range (unless otherwise specified). absolute maximum ratings note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltages referenced to vss = 0v vdd........................ vee................ supply voltage vdd-35v to 0v 0v to 7v voltage at any input, except lcd ..-0.3 to vdd+0.3v ? voltage at input...............vdd-35 to vdd+0.3v lcd? dc current any input pin...................................10 ma power dissipation......................................................300 mw operating temperature range - hi-temp/mil..-55 to +125c storage temperature range...........................-65 to +150c operating temperature range - industrial........-40 to +85c holt integrated circuits 3 cascading - ext. oscillator din hi-8010j-85 cs lcd? cl ld dout bp segments 1-32 din hi-8010j-85 cs lcd? cl ld dout bp segments 33-64 din hi-8010j-85 cs lcd? cl ld dout bp segments 65-96 back plane ld cl cs figure 2 cascading - rc oscillator din hi-8110pqi cs lcd? cl ld dout bp segments 1-38 lcd? opt din hi-8110pqi cs lcd? cl ld dout bp segments 39-76 lcd? opt din hi-8110pqi cs lcd? cl ld dout bp segments 77-114 lcd? opt back plane 470pf 150k ld cl cs figure 3
hi-8010/hi-8110 series holt integrated circuits 4 parameter symbol vdd min typ max units cl clock period t 5v 1200 ns clock pulse width t 5v 520 ns data in - setup t 5v 50 ns data in - hold t 5v 400 ns chip select - setup to clock t 5v 200 ns chip select - hold to clock t 5v 450 ns load - setup to clock t 5v 500 ns chip select - setup to load t 5v 300 ns load pulse width t 5v 500 ns chip select - hold to load t 5v 300 ns cw ds dh css csh ls csl lw lcs data out valid, from clock t 5v 800 ns cdo ac electrical characteristics vdd = 5v, vee = -25v, vss = 0v, ta = operating temperature range (unless otherwise specified). timing diagram t csh t css t ds t dh t cl t cdo t ls t lw t csl t lcs cl input din input cs input ld input dout output valid valid valid valid valid
hi-8010/hi-8110 series holt integrated circuits 5 additional hi-8010/hi-8110 pin configurations (see page 1 for the 52-pin plastic qfp) 39 38 37 36 35 34 33 32 31 30 29 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 v ee s27 s28 s29 s30 s31 s32 n/c v ld ss cs cl 7 8 9 10 11 12 13 14 15 16 17 s26 s25 s24 s23 s22 s21 s20 dout 32 bp s19 s18 din lcd? lcd?opt v s1 s2 s3 s4 s5 s6 s7 dd 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 hi-8010j-85 & hi-8110j-85 44 - pin plastic plcc hi-8010sm-36 & hi-8110sm-36 40 - pin ceramic lcc 543214039383736 s25 s24 s23 s22 s21 s20 dout 30 bp s19 s18 16 17 18 19 20 21 22 23 24 25 6 7 8 9 10 11 12 13 14 15 35 34 33 32 31 30 29 28 27 26 lcd?opt v s1 s2 s3 s4 s5 s6 s7 s8 dd lcd? din ld v s30 s29 s28 s27 s26 cl ss s9 s10 s11 s12 s13 s14 v s15 s16 s17 ee hi-8010sm-32 & hi-8110sm-32 48 - pin ceramic lcc 6 5 4 3 2 1 48 47 46 45 44 43 19 20 21 22 23 24 25 26 27 28 29 30 s28 s27 s26 s25 s24 s23 s22 s21 s20 dout 38 bp s19 lcd? lcd?opt v s37 s38 s1 s2 s3 s4 s5 s6 s7 dd din ld v s36 s35 s34 s33 s32 s31 s30 s29 cl ss s8 s9 s10 s11 s12 s13 s14 v s15 s16 s17 s18 ee 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32
hi-8010/hi-8110 series holt integrated circuits 6 ordering information hi - j - 85 (44-pin plastic j lead - plcc) 8x10 x part number lead finish 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank hi - (ceramic leadless chip carrier - lcc) 8x10sm -xx input logic number of segments 8110sm cmos 30 ttl 38 part number master/ slave flow burn in lead finish tin / lead (sn / pb) solder -36 both m yes tin / lead (sn / pb) solder -32 both m yes part number input logic 8110pq cmos 8010pq ttl part number temperature range -55c to +125c -55c to +125c temperature range flow burn in -40c to +85c no i -40c to +85c no i part number input logic number of segments master/ slave 8110 cmos 32 both 8010 ttl 32 both hi - (52-pin plastic quad flat pack - pqfp) 8x10pq x x part number lead finish 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank temperature range flow burn in -40c to +85c no i -55c to +125c no t part number number of segments master/ slave t 38 both i 38 both 8010sm number of leads 40 48
holt integrated circuits 7 hi-8010/hi-8110 series semi-custom packaging the above part numbers represent the standard configurations of the hi-8010 & hi-8110 products. they can also be provided with a varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide variety of packages. listed below are currently available packages. please contact the holt sales department for your specific requirements. package # description leads plastic dual-in-line (pdip) 40 48 plastic quad flat pack (pqfp) 52 plastic j-lead chip carrier (plcc) 44 ceramic dual-in-line (cdip) 40 48 ceramic leadless chip carrier (lcc) 40 48 ceramic j-lead chip carrier 44 48 ceramic leaded chip carrier 40 48
package type: pin no. 1 ident .045 x 45 .050 .005 (1.27 .127) .045 x 45 pin no. 1 44-pin plastic plcc see detail a .172 .008 (4.369 .203) detail a .020 min (.508 min) .025 .045 r .690 .005 (17.526 .127) sq. .610 .020 (15.494 .508) .031 .005 (.787 .127) .653 .004 (16.586 .102) sq. .017 .004 (.432 .102) .015 .002 (.381 .051) .009 .011 44j hi-8010/hi-8110 package dimensions inches (millimeters) package type: 52pqs 52-pin plastic quad flat pack holt integrated circuits 8 .008 (0.20) min. .032 .088 .175) (1.6 typ. .394 sq. .10) .004 0 7 .009 .003r (.225 .075r) d etail a .009 r typ (0.23 r typ) .079 (2.00 .05) .002 see detail a (10.00 .092 .004 (2.32 .12) (.88 .15) .012 .003 (.30 .08) .035 .006 .0256 bsc (0.65 bsc) .520 .010 (13.2 .25) sq.
p ackage t ype : package type: 40-pin ceramic leadless chip carrier 40s 48-pin ceramic leadless chip carrier 48s hi-8010/hi-8110 package dimensions inches (millimeters) holt integrated circuits 9 pin 1 ident. .484 .009 (12.294 .228) sq. pin 1 ident. .085 max. (2.159 max.) .044 .011 (1.118 .280) .020 .003 (.508 .076) .040 003 (1.016 .076) pin 1 ident. (2.286 max.) .090 max. .040 .007 (1.016 .178) pin 1 ident. .020 typ. (.508 typ.) .040 typ. (1.016 typ.) .563 .009 (14.300 .228) sq.
|
